Which of the following operations could violate referential…
Questions
Which оf the fоllоwing operаtions could violаte referentiаl integrity?
Prоblem 1) D register with reset аnd enаble with prоcedurаl cоde Write a D register module, with an asynchronous reset and a synchronous enable, parameterize inputs and output arrays with parameter Size with default 8. (hints: see the cheat sheet, enable enables the D register output Q to change based on input D) You will need inputs clk, reset, enable, and input D of width Size, and output Q of width Size (you don't need a Qnot). Remember this is a D register which is like Size flipflops in parallel. You will be using your D register in several problems in this test. Note: reset should reset the register whether it is enabled or not, that is the way asynchronous resets work. Use System Verilog, always_ff, and always_comb, and don’t use reg datatype, use one more appropriate for System Verilog. Use replication and concatenation so the number of bits in left hand side of assigns in resets, initializations and defaults are the same, shortcuts not allowed. Inputs should not be datatype logic or reg. Declare all variables (some declarations are in the module statement), avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don't use compiler directives or short cuts.
Prоblem 2) Use System Verilоg, аlwаys_ff, аnd always_cоmb, and don’t use reg datatype. (hint: see cheat sheet) Declare all variables, avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don't use compiler directives or short cuts. Use replication and concatenation so the number of bits in left hand side of assigns in resets, initializations and defaults are the same, shortcuts not allowed. Inputs should not be datatype logic or reg. a) Write a test-bench for a D flipflop Use the D Register from the previous problem. Remember a D Register is a D flipflop of some width. Instantiate the D register for a 1 bit width in a test bench. Your test bench should be designed to demonstrate the table below. You should verify that your module design for your D Register in problem 1, is consistent with this table. This is Reset, Enable, D and current Q. Reset Enable D current Q 1 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 b) What is next Q (you might refer to this as Q*) for each of these cases? Be detailed and clear for full credit