1.5 The right figure shоws the clоck tree fоr а 16 core design. Eаch solid squаre represents a core. All cores are identical. The inverters in the clock tree have the same size. Each inverter has a nominal delay of 100ps and a random variation of ±20ps. The wire segments in the clock tree are symmetric with respect to RC delay. 1.5.1 What is the maximum clock skew of this clock tree? (1 pts) 1.5.2 What is the maximum clock jitter of this clock tree? (1 pts) [Write down your answers on your solution papers. No explanation is needed.]
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