Instructiоns Answer eаch оf the exаm prоblems shown below on your printed аnswer sheet. Write your answers clearly. For problems 2-5, to receive credit or partial credit, you must show your work. Draw a box around your final answer. Problem 1 When majority carriers pile up at the oxide-Si interface, what is the bias condition? Accumulation. Flat-band. Depletion. Deep depletion. Inversion. What is important about the condition, ({psi _S} = 2{psi _B})? It is the flat-band condition. It is the boundary between accumulation and depletion. It is the boundary between depletion and inversion. It is the boundary between accumulation and inversion. It is the condition for which the semiconductor is intrinsic at the surface. How does the width of the depletion region vary with surface potential? As (left| {{psi _S}} right|) As ({left| {{psi _S}} right|^{1/2}}) As ({left| {{psi _S}} right|^0}) As ({left| {{psi _S}} right|^{ - 1/2}}) As ({left| {{psi _S}} right|^{ - 1}}) What is the physical meaning of the term, (-Q_S(psi_s)/C_{ox})? It is the voltage drop across the semiconductor. It is the voltage drop across the semiconductor-oxide interface. It is the voltage drop across the inversion layer. It is the voltage drop across the oxide. It is the metal-semiconductor work function difference. For ({V_G} > {V_T}), additional increases in gate voltage increase the surface potential very little (i.e. the surface potential stays at about (2{psi _B})). Why? Because most of the increase in gate voltage increases the volt drop across the semiconductor. Because most of the increase in gate voltage increases the volt drop across the oxide. Because "deep depletion" occurs. Because avalanche breakdown limits the potential drop across the semiconductor. Because of strong Zener tunneling. Consider an MOS-C in equilibrium with an N-type semiconductor and a metal gate with a workfunction smaller than the semiconductor. Which of the following is true about the semiconductor? It is at the flat-band condition. It is in accumulation. It is in deep depletion. It is in breakdown. It is in depletion or inversion depending on the magnitude of ({Phi _M} - {Phi _S}). How are "high" and "low -frequency" MOS C-V characteristics different? In accumulation, the high-frequency cap is lower than the low-frequency cap. At flat-band, the high-frequency capacitance is lower than the low-frequency cap. In depletion, the high-frequency capacitance is lower than the low-frequency cap. In depletion, the high-frequency capacitance is higher than the low-frequency cap. In inversion the high-frequency capacitance is lower than the low-frequency cap. Which of the following is true about the mobile electron charge in C/cm2 in a P-type semiconductor? There is no mobile charge for ({V_{GS}} < {V_T}). The mobile charge varies as (e^{q^{V_{GS}/{k_BT}}}) below and above threshold. The mobile charge varies as (e^{q^{V_{GS}/{mk_BT}}}) below and above threshold. The mobile charge varies as (e^{q^{V_{GS}/{mk_BT}}}) below threshold and as (left( {{V_{GS}} - {V_T}} right)) above threshold. The mobile charge varies as (left( {{V_{GS}} - {V_T}} right)) below threshold and as (e^{q^{V_{GS}/{mk_BT}}}) above threshold. As we reduce the channel length of a MOSFET without changing anything else, what three effects occur? DIBL decreases, SS increases, punch-through voltage decreases. DIBL increases, SS increases, punch-through voltage decreases. DIBL decreases, SS decreases, punch-through voltage decreases. DIBL increases, SS decreases, punch-through voltage decreases. DIBL decreases, SS increases, punch-through voltage increases. How are the on-current and off-current of a MOSFET related? A linear increase in on-current will give a linear increase in off-current. An exponential increase in on-current will give a linear increase in off-current. A linear increase in on-current will give an exponential increase in off-current. A linear increase in on-current will give a linear decrease in off-current. An exponential increase in on-current will give a linear decrease in off-current. Problem 2 (20 points) This problem is about the MOS capacitor whose energy band diagram is shown below. The semiconductor is silicon at 300K with ({n_i} = {10^{10}};{rm{c}}{{rm{m}}^{{rm{ - 3}}}}), and the insulator is SiO2 with a relative dielectric constant of 3.9 and a thickness of 2 nm. Also assume that the electrostatic potential in the silicon is zero as (x to infty ). There is no fixed charge at the insulator-silicon interface. What is the volt drop across the semiconductor? What is the flatband voltage of this MOS capacitor? Problem 3 (20 points) Consider a silicon MOSFET at room temperature with the following parameters. (W = 1 times {10^{ - 4}};{rm{cm}}) ({V_T} = 0.25;{rm{V}}) at ({V_{DD}} = 1.0;{rm{V}}) ({R_{SD}} = {R_S} + {R_D} = 220;Omega - mu {rm{m}}) ({upsilon _T} = sqrt {frac{{2{k_B}T}}{{pi {m^*}}}} ;{rm{ = 1}}{rm{.23}} times {rm{1}}{{rm{0}}^7};{rm{cm/s}}) ({C_{inv}} = 1.9 times {10^{ - 6}};{rm{F/c}}{{rm{m}}^{rm{2}}}) ({mu _n} = 175;{rm{c}}{{rm{m}}^{rm{2}}}{rm{/V - s}}) Answer the following two questions about this MOSFET. What is the mean-free-path for backscattering in a long channel version of this MOSFET? For L = 22 nm, what apparent mobility would be measured? Problem 4 (20 points) Consider a silicon MOSFET at room temperature with the same parameters as in Prob 3). (W = 1 times {10^{ - 4}};{rm{cm}}) ({V_T} = 0.25;{rm{V}}) at ({V_{DD}} = 1.0;{rm{V}}) ({R_{SD}} = {R_S} + {R_D} = 220;Omega - mu {rm{m}}) ({upsilon _T} = sqrt {frac{{2{k_B}T}}{{pi {m^*}}}} ;{rm{ = 1}}{rm{.23}} times {rm{1}}{{rm{0}}^7};{rm{cm/s}}) ({C_{inv}} = 1.9 times {10^{ - 6}};{rm{F/c}}{{rm{m}}^{rm{2}}}) ({mu _n} = 175;{rm{c}}{{rm{m}}^{rm{2}}}{rm{/V - s}}) Answer the following two questions about this MOSFET. Assume an L = 22 nm version of this MOSFET. What is the injection velocity? You may assume that it is a well-designed MSOFET with a bottleneck region that is 10% of the channel length. What is the on-current for this transistor? Problem 5 (20 points) The IV characteristics for 14 nm N- and P-MOSFETs are shown below. Assume W = 1 micrometer, that the gate capacitance in strong inversion is (C_{inv} = 2.0 {mu} F/cm^2), and the series resistance are ({R_S} = {R_D} = 50;Omega ). You may also assume that ({V_{TN}} = left| {{V_{TP}}} right| = 0.2)V. The linear region current of the N-MOSFET is given by({I_{DLIN}} = frac{W}{L}{mu _n}{C_{inv}}left( {{V_{GS}} - {I_D}{R_S} - {V_{TN}}} right)left[ {{V_{DS}} - {I_D}left( {{R_S} + {R_D}} right)} right])What is the corresponding expression for the P-MOSFET? Note that ID > 0 for current flowing into the drain of the N-MOSFET and ID > 0 for current flowing out of the drain of the P-MOSFET. What is the approximate number of holes per cm2 at the virtual source under on-current conditions for the P-MOSFET? Congratulations! You are almost done with this exam. DO NOT end the Honorlock session until you have submitted your work to Gradescope. Submission Instructions Use your phone to scan your answer sheet and save it as a PDF. Make sure your scan is legible! Email the PDF to yourself or save it to the cloud (Google Drive, etc.). Click the following link to submit your work to Gradescope: Link to Gradescope Select Exam 2 Follow the prompts to upload your PDF. Match the problems to your pages. Return to this window, agree to the Honor Statement, and click the Submit Quiz to end the exam and end the Honorlock session.
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