M.E. Lock The context for this question is the same as the p…

M.E. Lоck The cоntext fоr this question is the sаme аs the previous question. Given:  32-core cаche-coherent bus-based multiprocessor  Invalidation-based cache coherence protocol  Architecture supports atomic "Test-and-set (T&S)", atomic "Fetch-and-add (F&inc)", and atomic "fetch-and-store (F&St)" operations. All these operations bypass the cache.  An application has 32 threads, one on each core.   ALL threads are contending for the SAME lock (L)  Each lock acquisition results in 100 iterations of the spin loop for each thread  The questions are with respect to the following spin-lock algorithms (as described in the MCS paper, and restated below for convenience):  Spin on Test-and-Set: The algorithm performs a globally atomic T&S on the lock variable “L”  Spin on Read: The algorithm, on failure to acquire the lock using T&S, spins on the cached copy of “L” until notified through the cache coherence protocol that the current user has released the lock.  Ticket Lock: The algorithm performs “fetch_and_add” on a variable “next_ticket” to get a ticket “my_ticket”. The algorithm spins until “my_ticket” equals “now_serving”.  Upon lock release, “now_serving” is incremented to let the spinning threads that the lock is now available.  MCS lock: The algorithm allocates a new queue node, links it to the head node of Lock queue using “fetch-and-store”, sets the “next” pointer of the previous lock requestor to point to the new queue node, and spins on a “got_it” variable inside the new queue node if the lock is not immediately available (i.e., the Lock queue is non-empty). Upon lock release, using the “next” pointer, the next user of the lock is notified that they have the lock.   d) [2 points] This pertains to the “MCS lock” algorithm. Answer True/False with justification. No credit without justification. At lock release, if the “next” pointer is “nil” it is safe for the MCS lock algorithm to assume that there are no other threads waiting for this lock.