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Structural architectures describe the system as a collection of components that are interconnected to perform a function

Multiple process blocks run concurrently with relation to each other

Fill in the following code for the behavioral architecture of an ALU using the numeric standard library. Write the correct code for each region as specified by the comments around regions. library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity example is       generic (width : positive := 4); –width will ALWAYS be even       port (             in1      : in std_logic_vector(width-1 downto 0);             in2      : in std_logic_vector(width-1 downto 0);             sel      : in std_logic_vector(1 downto 0);             out1     : out std_logic_vector(width-1 downto 0);             out2    : out std_logic_vector(width-1 downto 0);             overflow : out std_logic       );end example;architecture BHV of example isbegin                  — REGION 1: Write what goes in the process list below —       process(    )             –variables list – no need to write anything here             variable temp_add  : unsigned(width downto 0);             variable temp_mult : unsigned(2*width-1 downto 0);       begin             — REGION 2: Initialize any signals below —                       case sel is                            –for region 3 compare: if in1 greater than in2 subtract in1 by in2                      –if not add and set the overflow bit as width. set both outputs in out1                    when “00” => — REGION 3: Write code below —                      –for region 4 compare: if in1 is equal to “1111” then ‘and’ in1 and in2 and set the result to out1.                      –Then elsif in2 is equal to “0000” then ‘or’ in1 and in2 and set the result to out2                      — You can assume the width is 4 he and if neither true, set out2 to in1                    when “01” =>                         — REGION 4: Write code below –-                             –multiply: store high bits in out2 and low bits in out1. keep in mind, the width generic                 –will always be even (no need to account for an extra bit on out out1 or out2)                    when “10” =>                         — REGION 5: Write code below –-                                             –create the last when statement that accounts for all other cases and set out1 to 0              — REGION 6: Write code below —             end case;                   end process;end BHV;

Answer the following questions and clearly label each answer (a) Define the logic for the carry out c3 of a carry look-ahead adder (CLA) in terms of the propagate signals (pi), generate signals (gi), and carry in (c0).     b) What type of relationship exists between a ripple carry adder’s area and width?     c) What type of relationship exists between a carry look-ahead adder area and width?   d) What is the advantage of using a carry look-ahead adder over a ripple carry, assuming width is not aconstraint/issue?

For generates represent patterns in behavioral descriptions

A single assignment to all outputs at the beginning of a process for combinational logic will guarantee there are no latches for that logic

Fill in the VHDL to implement the illustrated circuit. Assume that clk and rst connect to every register in the schematic. All wires/operations are width bits except for in4, which is a single bit. Ignore adder overflow. Assume the mux selects the left input when in4 = ‘1’. Use the next page if necessary.   — Write code in specified regions creating the diagram used above –library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity diagram is       generic (width : positive := 8);       port(              clk, rst : in std_logic;              in1, in2, in3 : in std_logic_vector(width-1 downto 0);              in4 : in std_logic;              out1, out2 : out std_logic_vector(width-1 downto 0));end diagram;architecture BHV of example is  –Region 1: Write code below initializing any signals here–begin process(clk, rst)      begin — Region 2: Write code —           elsif (rising_edge(clk)) then  — Region 3: Write Code —                      end if;  end process;– Region 4: Write Code –end BHV;

A single assignment to all outputs at the beginning of a process for combinational logic will guarantee there are no latches for that logic

Fill in the following code for the behavioral architecture of an ALU using the numeric standard library. Write the correct code for each region as specified by the comments around regions. library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity example is       generic (width : positive := 4); –width will ALWAYS be even       port (             in1      : in std_logic_vector(width-1 downto 0);             in2      : in std_logic_vector(width-1 downto 0);             sel      : in std_logic_vector(1 downto 0);             out1     : out std_logic_vector(width-1 downto 0);             out2    : out std_logic_vector(width-1 downto 0);             overflow : out std_logic       );end example;architecture BHV of example isbegin                  — REGION 1: Write what goes in the process list below —       process(    )             –variables list – no need to write anything here             variable temp_add  : unsigned(width downto 0);             variable temp_mult : unsigned(2*width-1 downto 0);       begin             — REGION 2: Initialize any signals below —                       case sel is                            –for region 3 compare: if in1 greater than in2 subtract in1 by in2                      –if not add and set the overflow bit as width. set both outputs in out1                    when “00” => — REGION 3: Write code below —                      –for region 4 compare: if in1 is equal to “1111” then ‘and’ in1 and in2 and set the result to out1.                      –Then elsif in2 is equal to “0000” then ‘or’ in1 and in2 and set the result to out2                      — You can assume the width is 4 he and if neither true, set out2 to in1                    when “01” =>                         — REGION 4: Write code below –-                             –multiply: store high bits in out2 and low bits in out1. keep in mind, the width generic                 –will always be even (no need to account for an extra bit on out out1 or out2)                    when “10” =>                         — REGION 5: Write code below –-                                             –create the last when statement that accounts for all other cases and set out1 to 0              — REGION 6: Write code below —             end case;                   end process;end BHV;

Which compound or compounds contain both ionic and molecular bonds? (i) K3N; (ii) PH3; (iii) NaClO2; (iv) ClO2; (v) AlF3