A given circuit has the following paths between flip-flops:…

A given circuit has the following paths between flip-flops: Path 1: 3.1 ns Path 2: 2.9 ns Path 3: 1.1 ns Path 4: 3.3 ns Assuming all flip-flops are in the same clock domain, what is the maximum clock frequency of this circuit ignoring setup & hold times? Specify your answer in MHz rounded to the nearest integer. (e.g.  the answer for 100.4 MHz should just be 100).

Which of the following assertions correctly verify an asynch…

Which of the following assertions correctly verify an asynchronous reset, where the following register’s output out is all 0s during the same cycle that reset is asserted? Select all that apply. Assume a 200 MHz clock.   module register  #(    parameter WIDTH    )   (    input logic              clk,    input logic              rst,    input logic              en,    input logic [WIDTH-1:0]  in,    output logic [WIDTH-1:0] out    );