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What is one way to reduce the Miss Penalty of a cache?

A SIMD processor can run any parallel program written for a MIMD processor.

Create an instruction stream with the following dependency graph. Recall that a regular arrow indicates a true dependence, a circle indicates an output dependence, and a cross indicates an anti-dependence.      Use only ADD instructions, and use the following format (the ID is the letter use for each instruction in the above diagram): ID: ADD DEST SRC1 SRC2    

In your own words, what is cache coherency and why do we care about it? No need to give the full definition, just explain what it is, and why it is useful for a shared memory system to to implement it.

You respond to the report of a 65-year-old female patient complaining of difficulty breathing. Upon your arrival, you find the patient seated in a tripod position in moderate respiratory distress. The patient advises she has a lifetime history of asthma and cannot receive relief with her albuterol treatment. The patient, and the patient’s husband, advises she was recently diagnosed with hypertension. They both advise they cannot afford new medications, so the patient has been taking her husband’s propanolol to control her hypertension. To receive full credit, you must answer the following questions: 1. What are the receptors of the sympathetic nervous system? 2. Explain in your own words if propanolol is helping your patient or harming your patient. 3. Would your albuterol help this patient? 4. Would administering epinephrine help this patient? 5. Would Atrovent help this patient, and if so, how?

Fill in the tail and pause bits for the following VLIW schedule. The tail bits should be 0 or 1, and the pause value should be a non-negative integer or just a dash ‘-‘ (without the quotes) if it is not needed.   ADD MUL LD A B C    D E F   Instruction Tail? Pause A [AT] [AP] B [BT] [BP] C [CT] [CP] D [DT] [DP] E [ET] [EP] F [FT] [FP]

Cache Questions

At ACME computing, a computer architect comes up with a nifty device which when added to their premier CPU speeds up division instructions by 70 percent. How much faster will a program where 20 percent of instructions are division instructions will run with this modification (as compared to the unmodified CPU)?

Describe a scenario in which two instructions may be fired out of order but retired in order in the original Tomasulo algorithm.

Say we have a snoopy MSI cache protocol. We have three processors all accessing the same block of data. This is a write-invalidate cache. Initially, they all have the block in state I. If the following accesses are performed by each CPU, what is the final state of the cache? PE1: Write PE2: Read PE3: Read PE1: Write PE2: Write PE3: Read Fill M, S or I for each processor below: PE1: [1] PE2: [2] PE3: [3]