The arbiter is a component that is used to allocate a shared…

The arbiter is a component that is used to allocate a shared resource to only one component. Suppose that we have a priority arbiter design which takes N “request” signals as inputs and produces N “grant” signals as outputs.  Our arbiter has a fixed priority and it asserts only one grant signal based on the priority and the asserted request lines.    If Req[i] has priority over req[i-1], please Select the choice that precisely describe the following property in SystemVerilog: “At the posedge of the clock, if req[1] is asserted, eventually gnt[1] will be asserted for one clock cycle.