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Assume the code segment below is run on a 2-Issue wide, 4-st…

Assume the code segment below is run on a 2-Issue wide, 4-stage (IF, DISP, EX, SU) FICO pipelined processor with the following configuration. (Note, in the review on Wednesday we were referring to SU (State Update) as WB.) The processor can fetch 2 instructions per clock cycle The dispatch queue can hold 4 entries Has the following function units: 2 ADD Units (1 cycle latency) 1 MUL Unit (3 cycle latency, Pipelined) 1 Floating Point ADD Unit (2 cycle latency, Unpipelined) Note: This is used by FADD instructions Fill in the pipeline timing diagram for the given instruction trace executing on the above pipeline. Each blank should have either one of the stages (IF, DISP, EX, SU), or a single dash, ‘-‘, (without the quotes) if nothing goes in that spot. You may or may not need to use every cycle. A: ADD    R1, R2, R6 B: MUL    R3, R4, R5 C: FADD   R1, R2, R6 D: ADD    R2, R1, R3 E: MUL    R6, R7, R6 F: ADD    R3, R2, R1 0 1 2 3 4 5 6 7 8 9 A [A0] [A1] [A2] [A3] [A4] [A5] [A6] [A7] [A8] [A9] B [B0] [B1] [B2] [B3] [B4] [B5] [B6] [B7] [B8] [B9] C [C0] [C1] [C2] [C3] [C4] [C5] [C6] [C7] [C8] [C9] D [D0] [D1] [D2] [D3] [D4] [D5] [D6] [D7] [D8] [D9] E [E0] [E1] [E2] [E3] [E4] [E5] [E6] [E7] [E8] [E9] F [F0] [F1] [F2] [F3] [F4] [F5] [F6] [F7] [F8] [F9]