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Problem 2) Use System Verilog, always_ff, and always_comb, a…

Problem 2) Use System Verilog, always_ff, and always_comb, and don’t use reg datatype. (hint: see cheat sheet) Declare all variables, avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don’t use compiler directives or short cuts. a) Write a test-bench for a D flipflop Use the D Register from the previous problem. Remember a D Register is a D flipflop of some width. Instantiate the D register for a 1 bit width in a test bench. Your test bench should be designed to demonstrate the table below. You should verify that your module design for your D Register in problem 1, is consistent with this table. This is Reset, Enable, D and current Q. Reset  Enable D current Q 1 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1   b) What is next Q (you might refer to this as Q*) for each of these cases?  Be detailed and clear for full credit