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Problem 1) D register with reset and enable with procedural…

Problem 1) D register with reset and enable with procedural code Write a D register module, with an asynchronous reset and a synchronous enable, parameterize inputs and output arrays with parameter Size with default 8. (hints: see the cheat sheet, enable enables the D register output Q to change based on input D) You will need inputs clk, reset, enable, and input D of width Size, and output Q of width Size (you don’t need a Qnot). Remember this is a D register which is like Size flipflops in parallel. You will be using your D register in several problems in this test. Note: reset should reset the register whether it is enabled or not, that is the way asynchronous resets work. Use System Verilog, always_ff, and always_comb, and don’t use reg datatype, use one more appropriate for System Verilog. Declare all variables (some declarations are in the module statement), avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don’t use compiler directives or short cuts.  

Problem 5) FSM Write a finite state machine System Verilog m…

Problem 5) FSM Write a finite state machine System Verilog module named FSM. Finite State Machines are not parameterized, because the number of states is set by the problem. Use the state transition table below (which contains the same information as a state diagram). You only need this state transition table to build the FSM. Remember Z is purely combinatorial. Do not use an enumerated type for this problem (if you don’t know what that is, you shouldn’t worry about it). Use a localparam to do a state assignment and then use the names in your code rather than numbers. Use a standard Finite state machine design organized in parts  a, b, c, … below. Inputs must be x, reset, clk, and outputs must be State, and Z. This should be done by instantiation of register you have already designed in a previous problem (the D Register) and instantiation of MUX41 described below. Be sure to instantiate the MUX both for determining the next state and in another instance to determine the output Z. module MUX41 #(parameter S=6) (input [S-1:] A, B, C, D, input [1:0] Sel, output logic [S-1:0] Y); … endmodule Don’t complete this MUX just instantiate it, you will not get extra credit for completing the MUX. For maximum credit your code should carefully follow the specification, and your grade will depend that. Use the minimum number of lines to accomplish this specification, and be succinct and well organized. Also use proper indentation for organization. If you duplicate the function of instances in procedural code it will be counted incorrect. Use System Verilog, always_ff, and always_comb, and don’t use reg datatype. (hint: see cheat sheet) Declare all variables, avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don’t use compiler directives or short cuts. next_state output Z State x=0 x=1 x=0 x=1 S0 S0 S1 1 0 S1 S2 S1 0 1 S2 S0 S3 1 1 S3 S3 S3 1 0 For full credit label each part of your solution a., b., or c. a. What Finite State Machine model are you using in this problem?   b. Module statement and declarations and localparam   c. Synchronous part using registers (in my solution this is 1 line)   d. Combinatorial part using mux from previous problem (in my solution this is 2 lines) to determine the next state,   e. Combinatorial part using mux to determine the output Z.   for full credit follow all directions