Problem 2) Use System Verilog, always_ff, and always_comb, a…

Problem 2) Use System Verilog, always_ff, and always_comb, and don’t use reg datatype. (hint: see cheat sheet) Declare all variables, avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don’t use compiler directives or short cuts. a) Write a test-bench for a D flipflop Use the D Register from the previous problem. Remember a D Register is a D flipflop of some width. Instantiate the D register for a 1 bit width in a test bench. Your test bench should be designed to demonstrate the table below. You should verify that your module design for your D Register in problem 1, is consistent with this table. This is Reset, Enable, D and current Q. Reset  Enable D current Q 1 0 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 b) What is next Q (you might refer to this as Q*) for each of these cases?  Be detailed and clear for full credit

A nurse is caring for a client who has a deep vein thrombosi…

A nurse is caring for a client who has a deep vein thrombosis and is prescribed heparin 1,200 units. Available is Heparin 25,000 units in 500 mL D5W. The many milliliters (mL) will the client receive? Numeric answers only. Round to the nearest whole number if indicated.  [CLOZE_01]