Blog

Problem 5) FSM Write a finite state machine System Verilog m…

Problem 5) FSM Write a finite state machine System Verilog module named FSM. Finite State Machines are not parameterized, because the number of states is set by the problem. Use the state transition table below (which contains the same information as a state diagram). You only need this state transition table to build the FSM.  Remember Z is purely combinatorial. Do not use an enumerated type for this problem (if you don’t know what that is, you shouldn’t worry about it). Use a localparam to do a state assignment and then use the names in your code rather than numbers. Use a standard Finite state machine design organized in parts a, b, c, … below. Inputs must be x, reset, clk, and outputs must be State, and Z. This should be done by instantiation of register  you have already designed in previous problems. Be sure to instantiate the MUX shown below both for determining the next state and in another instance to determine the output Z. You do not have to complete the mux, and won’t get extra credit for completing it. module MUX81 #(parameter S=6) (input [S-1:] A, B, C, D, E, F, G, H, input [2:0] Sel, output logic [S-1:0] Y); … endmodule For maximum credit your code should carefully follow the specification, and your grade will depend that. Use the minimum number of lines to accomplish this specification, and be succinct and well organized. Also use proper indentation for organization. If you duplicate the function of instances in procedural code it will be counted incorrect. Use System Verilog, always_ff, and always_comb, and don’t use reg datatype. (hint: see cheat sheet) Declare all variables, avoid errors or warnings that would occur during compilation, simulation or synthesis. Indent all blocks for full credit. Your code should be efficient and succinct. Don’t use compiler directives or short cuts. next_state State x=0 x=1 output Z S0 S0 S1 0 S1 S1 S2 0 S2 S1 S3 1 S3 S4 S0 0 S4 S1 S2 1 For full credit label each part of your solution a., b., or c. a. What Finite State Machine model are you using in this problem?   b. Module statement and declarations and localparam   c. Synchronous part using registers (in my solution this is 1 line)   d. Combinatorial part using mux from previous problem (in my solution this is 2 lines) to determine the next state,   e. Combinatorial part using mux to determine the output Z.   for full credit follow all directions

GREETINGS! You’ve reached the last question of the exam (or…

GREETINGS! You’ve reached the last question of the exam (or you’ve scrolled ahead) – well done! The proctoring team will review your exam recording and confirm that your exam was conducted without unauthorized aid, that there were no issues with acquiring solid recordings of you and your computer screen. Grades will be posted once the recordings are reviewed and I review the class’ performance on each question (I award points back when the correct answer is not selected by the majority of the class). Questions and answers to exams are not published in this course; there is no exam review in the hybrid APK 2105c class. Sharing exam content with others is not permitted. Please submit your exam now. If you fail to submit the exam by the time your exam access ends (i.e. 8:15 AM EST), the exam should be auto-submitted and uploaded to Canvas within 5 minutes. Again, well done on getting through this test! :]