Identify any violations of synthesis coding guideline for co…

Identify any violations of synthesis coding guideline for combinational logic. Explain the effect on the resulting synthesized circuit. library ieee;use ieee.std_logic_1164.all;entity example1 is   port (       a, b, c, d : in std_logic;       e, f, g    : out std_logic);end example1;architecture bhv of example1 isbegin   process(a,b,c)   begin       if (a = ‘1’) then           e