For coding problems write the code to have no compile, simulation, or synthesis errors. Declare all variables. Write your code in Verilog or System Verilog. Write your code with good organization. If you have blocks indent them for full credit. Your answer must be complete and clear. If you use System Verilog clearly state you are using it for credit. Your code should be efficient, succinct (about the minimum number of lines). Do not use compiler directives, and if you don’t know how to do that don’t worry about it. a) Write a full adder module named FA that adds single bit input A and B and carry in C and places this in output S. The carry out should be named Cout. Remember that S = A^B^C, and Cout is 1 if any two of A, B, and C are 1. b) Write a positive edge triggered SR flipflop module named SRff. You need inputs S, R, and clk, and output Q. Use only these inputs and outputs in your solution. If S=R=1 make output Q equal to 1’bx. This assigns Q to undefined when S and R are true at the same time to identify (in simulation) when this error has occurred. For full credit, the solution must use a fully simplified Boolean expression for Q. Note there is a SR flipflop table in the cheat sheet that you can use to derive the Boolean Expression. Remember Q is both the output (we call this Q* for Q later in time) and an input (this is the current Q). Hints: The solution should use an always with sensitivity to the positive edge of the clock clk.
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The Norfolk Four Case is an example of
The Norfolk Four Case is an example of
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