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A system uses linear page tables and has the following parameters: Address Space size: 32KB Physical Memory size: 64KB Page size: 4KB   A process that is currently running on the system has the following page table base register and page table as shown below.  Note, only 5 bits of every PTE are shown.  The full size of a PTE is 1 byte. PTBR: 0x2004 The process’s instructions and virtual addresses are: 0x0000 movl 0x1100, %edi  (load x)0x0008 addl $0x1, %edi    (add 1)0x000C movl %edi, 0x1100  (store x)

What is the largest VA for this process that will not cause any faults?

The portion of trap.h and syscall.h files for xv6 are shown in the table below.

CS 537: Introduction to Operating Systems Fall 2024: Midterm Exam #1   This exam is closed book, but you may use 1 sheet of notes.   No calculators may be used.   You have 1 hour and 30 minutes to complete this exam. Unless stated (or implied) otherwise, you should make the following assumptions: The OS manages a single uniprocessor (single core) All memory is byte addressable Page table and page directory entries require 4 bytes Data is allocated with optimal alignment, starting at the beginning of a page Assume leading zeros can be removed from numbers (e.g., 0x06 == 0x6). Hex numbers are represented with a proceeding “0x” The following might help you with some calculations: 0x100 = 28 = 256 210 = 1024 212 = 4096 210 bytes = 1KB 220 bytes = 1MB   This exam has 60 questions.  Each question has the same number of points.   Good luck!

On the same system, how many pages are there in the virtual address space of a process?

Processes and Scheduling

The purpose of the ASID in a TLB entry is to reduce the size of a process’ page table.

The purpose of the TLB is to speed address translation.

Sparsely used address spaces are poor candidates for multi-level page tables.

What will be the first TLB hit with the same TLB size and replacement policy as before?