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The purpose of the ASID in a TLB entry is to reduce the size of a process’ page table.

The purpose of the TLB is to speed address translation.

Sparsely used address spaces are poor candidates for multi-level page tables.

What will be the first TLB hit with the same TLB size and replacement policy as before?

For the same address space size, having smaller pages means you will have smaller page tables.

Convert the VA 0x7011 to its PA.

A page table entry holds the virtual page number for a given physical page.

What is the largest VA for this process that will not cause any faults and be in the heap segment?

In C an array is stored in row-major format. For example, an integer array of shape 4×4 with data like the one is shown in Figure 2 in memory as shown in Figure 3. Assume there is a tiny address space where each page is of 8 bytes and there are 16 such pages. We have a 4×4 array and the element a[0] is located at virtual address 20. (Virtual Page Number=02, offset = 04). Assume size of integer is 4 bytes   Consider the following function:   void print_array(int *arr, int cols, int rows){   for (size_t i=0; i

For a segment that grows negatively, if a VA’s offset is out-of-bounds then a page fault will occur.