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Processes and Scheduling

The purpose of the ASID in a TLB entry is to reduce the size of a process’ page table.

Sparsely used address spaces are poor candidates for multi-level page tables.

If the TLB size was increased to 8 entries, the TLB hit rate for the first function print_array would be:

A system uses linear page tables and has the following parameters: Address Space size: 32KB Physical Memory size: 64KB Page size: 4KB   A process that is currently running on the system has the following page table base register and page table as shown below.  Note, only 5 bits of every PTE are shown.  The full size of a PTE is 1 byte. PTBR: 0x2004 The process’s instructions and virtual addresses are: 0x0000 movl 0x1100, %edi  (load x)0x0008 addl $0x1, %edi    (add 1)0x000C movl %edi, 0x1100  (store x)

For the same address space size, having smaller pages means you will have smaller page tables.

When prog is executed how many times will the number 3 be printed?

What is the largest VA for this process that will not cause any faults and be in the heap segment?

A page table entry holds the virtual page number for a given physical page.

Virtual Addressing using Segmentation