Consider the following instruction breakdown that decomposes…

Consider the following instruction breakdown that decomposes an instruction into 4 parts: OPCODE DST SRC IMM OPCODE specifies the OPeration’s CODE.DST specifies a DeSTination register.SRC specifies a SouRCe register.IMM specifies a 2’s complement value (that’s IMMediately available as part of the instruction). Assume the architecture has 30-bit instructions, 18 opcodes, and 23 registers. A.) What is the minimum number of bits required to represent an OPCODE? [opcbits] B.) What is the minimum number of bits required to represent a register? [regbits] C.) What is the maximum number of bits that can be used to represent the IMM value? [immbits] D.) What is the largest positive value in base 10 that can represented by the IMM value? [immval]

Consider the following 6-state finite state machine, where t…

Consider the following 6-state finite state machine, where the states are labelled S1 – S6, the inputs are labelled 1 – 4 by the arrow’s tail, and the output is the letter under the state label: What is output when starting at state S4 and given the input sequence “2123”?The first letter is output from the starting state:[O1][O2][O3][O4][O5]

Consider the design of two logic circuits that both have fou…

Consider the design of two logic circuits that both have four inputs: A, B, C and D; and one output: X.  Each circuit is implemented using 4-input AND gates (with negated inputs) and an OR gate to generate the output. For circuit 1, X is defined to be 1 if and only if interpreting ABCD as an unsigned binary integer results in a number that is less than 4. Note A is the most significant bit, then B, and so on. For circuit 2, X is defined to be 1 if and only if interpreting ABCD as an unsigned binary integer results in an odd number. Note A is the most significant bit, then B, and so on. Which of the following 4-input gates would be used in the implementation of both circuits?FYI: Be certain; Canvas deducts points for incorrect choices.