Blog

For the same address space size, having smaller pages means you will have smaller page tables.

Convert the VA 0x7011 to its PA.

Now consider a function where we print the array contents in column order   void print_col_array(int *arr, int cols, int rows){    for(size_t i=0; i

Both the major and minor salivary glands are endocrine glands.

If the TLB size was increased to 8 entries, the TLB hit rate for the first function print_array would be:

On the same system, how many pages are there in the virtual address space of a process?

The purpose of the TLB is to speed address translation.

What will be the first TLB hit with the same TLB size and replacement policy as before?

A system uses linear page tables and has the following parameters: Address Space size: 32KB Physical Memory size: 64KB Page size: 4KB   A process that is currently running on the system has the following page table base register and page table as shown below.  Note, only 5 bits of every PTE are shown.  The full size of a PTE is 1 byte. PTBR: 0x2004 The process’s instructions and virtual addresses are: 0x0000 movl 0x1100, %edi  (load x)0x0008 addl $0x1, %edi    (add 1)0x000C movl %edi, 0x1100  (store x)

The purpose of the ASID in a TLB entry is to reduce the size of a process’ page table.