Blog

 If you are allowed to reorder these instructions, how would you reorder them to minimize the stalls?

I. Comprensión Auditiva [7 puntos]

Please give four features for CISC ISA.

In the simple 5-stage RISC processor, which stage completes the branch instruction? 

Now consider a case where the execution stage is slower and requires two cycles to complete.            That is, there are two execution stages, “(EXE)1” and “(EXE)2”.           Assume there is no extra structural hazards from the two execution stages.           For this CPU, how many cycles does it take to execute the above code?           Draw a pipeline diagram in the following table of its execution on this 6-stage RISC pipeline,           Moreover, in the box below, write the total number of cycles required to complete the above code.  Cycles   Pipeline executions:                                                                                                     CYCLE/ TIME   INSTRUCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MOV R1, [X] IF ID E1 E2 ME WB                                                                                                                                                                                                                                                                      

Why RISC processors have lower power consumption than CISC processors? 

What is the fundamental design philosophy difference between CISC and RISC?

True or False: most modern CPUs use RISC internally.

Scientific theories are also called models.

A Roberto no le gusta viajar.