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Consider Figure Q12 in the 12th question. Select one pipelin…

Consider Figure Q12 in the 12th question. Select one pipeline diagram that *CORRECTLY* showes in which cycle each of two MIPS instructions will be in each stage. The diagram below uses the classical 5-stage MIPS Pipeline presented in the textbook. The stages for the first instruction “lw $t2,4($t3)” are already given. You must consider that forwarding is done when it is possible to avoid a stall.   cycle 1 2 3 4 5 6 7 8 9 10 11 lw   $t2,4($t3) IF ID EX MEM WB sw   $t5,4($t2)

Assume a 2-way set associative data cache with (1) 2 cache s…

Assume a 2-way set associative data cache with (1) 2 cache sets,  (2) 2 words (8 bytes) per block (line), and (3) an LRU cache block replacement policy. For data writes, the data cache employs a write-back and write-allocate policy. As you did for MP8 data cache exercises, copy the following data memory reference table into your answer box, and fill  the remaining table with the appropriate data cache information for each memory reference. Memory Access Address in hex Cache Tag  Cache Set Index Byte Offset Result (hit/miss) # memory refs  4 bytes Read 0x58  5  1 0 miss 1 4 bytes Read 0x68 4 bytes Write 0x58 4 bytes Write 0x68 4 bytes Read 0x40 4 bytes Read 0xC    

Assume the values of integer variable “sum” is associated wi…

Assume the values of integer variable “sum” is associated with the registers $t2. Write MIPS assembly code to perform the following C/C++ if statement assuming $t5 is available. If needed, you can reference MIPS Green Sheet. if (sum < 0 && sum > 10)     sum = sum – 20;else     sum = sum + 10;