Virtualization_1a Full Virtualization   1. The above figure…

Virtualization_1a Full Virtualization   1. The above figure illustrates a memory translation scheme in a fully virtualized environment. In this setup, the Virtual Page Number (VPN) is first translated to a Physical Page Number (PPN), which is then mapped to a Machine Page Number (MPN). The guest OS page tables store the VPN-PPN mappings, while the shadow page table maintains the PPN-MPN mappings.    a. [2 points] How does the MPN differ from the PPN, and why is it needed?

Virtualization_1b Full Virtualization   The context for this…

Virtualization_1b Full Virtualization   The context for this question is the same as the previous question: 1. The above figure illustrates a memory translation scheme in a fully virtualized environment. In this setup, the Virtual Page Number (VPN) is first translated to a Physical Page Number (PPN), which is then mapped to a Machine Page Number (MPN). The guest OS page tables store the VPN-PPN mappings, while the shadow page table maintains the PPN-MPN mappings.    b. [1 points] Can you point out a glaring inefficiency in this scheme compared to a non-virtualized setting?

OS_Structure_4c Microkernel The context for this question is…

OS_Structure_4c Microkernel The context for this question is same as the previous question. 4. You are building an OS using a microkernel-based approach following the principles of the L3 microkernel. The processor architecture you are building this OS for has the following features:      • A 32-bit hardware address space.    • Paged virtual memory system (8KB pages) with a processor register called PTBR that points to the page table in memory to enable hardware address translation.     • A TLB with Address space IDs associated with each TLB entry.     • A pair of hardware-enforced segment registers (lower and upper bound of virtual addresses) which limit the virtual address space that can be accessed by a process running on the processor.     • A virtually-indexed physically tagged processor cache. You end up with 2 big subsystems (A and B) that each require 230 bytes of virtual memory space. You also end up with 4 subsystems (C,D,E,F) that require 100×220 , 500×220 , 1000×220 , and 2000×220 bytes of virtual memory, respectively. You want to put each of these subsystems in their own protection domains.  c. [2 points] (Answer this question based on your grouping of the protection domains) There is a context switch from A to B. What does your OS do to facilitate this context switch? 

Virtualization_2b Full Virtualization   The context for this…

Virtualization_2b Full Virtualization   The context for this question is the same as the previous question: 2. CPU virtualization mechanisms in a virtualized environment have two primary objectives. Providing each guest OS with the illusion of exclusive CPU ownership.  Delivering program discontinuity events to the guest OS.   b. [1 point] How are these events delivered to the guest OS in a fully virtualized setting?

Parallel_Systems_4 Barriers 4. [3 points] Consider the sens…

Parallel_Systems_4 Barriers 4. [3 points] Consider the sense reversing barrier implementation in C as follows where count, sense are shared variables which are initialized to N and False respectively. Will this code work? If yes explain why, if no, give brief reasoning and an example!