For the load instruction indicate which control wire are set…

For the load instruction indicate which control wire are set to low signal or high signal using the proper annotation. In your response, you don’t need to create a table, but do provide the name of control line and the signal next to it. Control Signal Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite    

In a pipelined processor architecture, various hazards can a…

In a pipelined processor architecture, various hazards can arise due to resource conflicts or data dependencies among instructions executing concurrently in different pipeline stages. One such hazard occurs when two instructions require the same hardware resource in the same clock cycle, potentially forcing one instruction to stall and wait for the other to complete its operation. What is the specific term used to describe this type of hazard, and what are the common strategies employed by modern processors to mitigate or resolve it?