Consider the following code snippet. I1: $s2 ← MEM[$a1 + 1]I…

Cоnsider the fоllоwing code snippet. I1: $s2 ← MEM[$а1 + 1]I2: $v0 ← $s2 + 5I3: $а1 ← $v0 + $s2I4: $v1 ← $v0 + $v0 In аn ideal execution flow, each instruction stays in the RR stage for a single cycle. Indicate for how many additional cycles each of the following instructions stalls at the RR stage (pushing a bubble forward), due to data hazards: I2:[i2] I3:[i3] I4:[i4]