Prоject: PLUS Design а 7-segment decоder thаt determines twо-bit logicаl input (using the switches on the BASYS 3 trainer board), and generates output on the 7-segment display as shown in the following table: S1 S0 7-segment Display 0 0 0 1 1 0 1 1 If both switches are OFF, the 7-segment has to display capital letter 'P'. If the switch S0 is ON and S1 is OFF, the 7-segment has to display capital letter 'L'. If the switch S0 is OFF and S1 is ON, the 7-segment has to display capital letter 'U'. If both switches are ON, the 7-segment has to display capital letter 'S'. To achieve this, you have to derive the Boolean expression for each segment of the 7-segment display: a, b, c, d, e, f, and g by using the method of your choice (Karnaugh map, minterm or maxterm). The 7-segment display on BASYS 3 board is active low, meaning... logical output 0 will turn ON the LED of that segment, logical output 1 will turn OFF the LED of that segment, For example, 7-segment Display a b c d e f g 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 0 0 Directions: Complete the truth table in question 1. Derive the Boolean expression for each segment and answer question 2. Implement your design on BASYS 3 Board using Xilinx Vivado with VHDL language. Provide your design code (.vhd) and constraints code (.xdc) in question 3 and 4, respectively. Take photos of your result and embed them to question 5. BASYS 3 MASTER XDC (constraints file template) https://github.com/Digilent/digilent-xdc/blob/master/Basys-3-Master.xdcLinks to an external site. (This is a new version of the constraints template in which you only need to enable one line of code for each port.
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